Implementation of a novel architecture for VLSI testing

Time, power, and data volume are among some of the most challenging issues for testing System-on-Chip (Soc.) and have not been fully resolved, even if a scan-based technique is employed. A novel architecture, referred to the Selective Trigger Scan architecture, is introduced in this paper to address these issues. This architecture reduces switching activity in the circuit-under-test (CUT) and increases the clock frequency of the scanning process. An auxiliary chain is utilized in this architecture to avoid the large number of transitions to the CUT during the scan-in process, as well as enabling retention of the currently applied test vectors and applying only necessary changes to them. It also permits delay fault testing. Using ISCAS 85 and 89 benchmark circuits, the effectiveness of this architecture for improving Soc. test measures (such as, time, and data volume) is experimentally evaluated and confirmed.