Title :
A HDL based reduced area NOC router architecture
Author :
Suraj, M.S. ; Muralidharan, D. ; Seshu Kumar, K.
Author_Institution :
SASTRA Univ., Thanjavur, India
Abstract :
In this work, we present the NOC router architecture with five port support which utilizes dual crossbar arrangement, the latency which arises due to the dual cross bar architecture is reduced by using predominant routing algorithm. This arrangement is more efficient and reduces about 10 % of device utilization.
Keywords :
hardware description languages; network routing; network-on-chip; HDL; device utilization; dual crossbar arrangement; five port support; predominant routing algorithm; reduced area NOC router architecture; Educational institutions; Field programmable gate arrays; Hardware design languages; Registers; Switches; NOC; crossbar; latency;
Conference_Titel :
Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), 2013 International Conference on
Conference_Location :
Tiruvannamalai
Print_ISBN :
978-1-4673-5300-7
DOI :
10.1109/ICEVENT.2013.6496593
