Title :
(Quasi-) linear path delay fault tests for adders
Author :
Becker, Bernd ; Drechsler, Rolf ; Reddy, Sudhakar M.
Author_Institution :
Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
Abstract :
We investigate the path delay fault testability of the adder function. A method to reduce the number of tests is presented and applied to several well-known hardware realizations, like the Carry Ripple Adder (CRA) and the the Carry Look Ahead Adder (CLA). Depending on the structure we obtain linear or quasi-linear, i.e. O(n) or O(n log n), respectively, size for a complete test of the whole adder with respect to its timing behavior, thus e.g. making feasible an on-line dynamic test for many adders currently in use
Keywords :
adders; delays; logic testing; adder; carry look ahead adder; carry ripple adder; linear path delay fault test; on-line dynamic test; quasilinear path delay fault test; timing; Adders; Circuit faults; Circuit testing; Computer science; Delay lines; Hardware; Manufacturing processes; Robustness; Timing; Very large scale integration;
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-8186-7755-4
DOI :
10.1109/ICVD.1997.567969
