• DocumentCode
    1927347
  • Title

    Delay fault coverage enhancement using multiple test observation times

  • Author

    Jone, Wen-Ben ; Ho, Yun-Pan ; Das, Sunil R.

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Nat. Chung-Cheng Univ., Chiayi, China
  • fYear
    1997
  • fDate
    4-7 Jan 1997
  • Firstpage
    106
  • Lastpage
    110
  • Abstract
    It has been demonstrated that delay fault coverage loss could be significant if improper propagation paths are used. This occurs when the delay test pair of a target propagation path cannot be effectively generated by an ATPG tool, or when stuck-at test patterns are used as transition (or gate) delay test patterns. In this work, an efficient method is proposed to reduce the amount of fault coverage loss by using multiple observation times. The basic idea is to offset the shorter propagation paths (really used) by tightening the observation times. Given a probability distribution of defect sizes and a set of slack differences, this method is able to locate several observation times that result in small fault coverage loss
  • Keywords
    combinational circuits; delays; fault diagnosis; logic testing; sequential circuits; ATPG tool; combinational circuits; defect size probability distribution; delay fault coverage enhancement; fault coverage loss reduction; gate delay test patterns; multiple test observation times; scan design methodology; sequential circuits; stuck-at test patterns; target propagation path; transition delay test patterns; Automatic test pattern generation; Circuit faults; Circuit testing; Clocks; Delay effects; Power system modeling; Probability distribution; Propagation delay; Sequential analysis; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1997. Proceedings., Tenth International Conference on
  • Conference_Location
    Hyderabad
  • ISSN
    1063-9667
  • Print_ISBN
    0-8186-7755-4
  • Type

    conf

  • DOI
    10.1109/ICVD.1997.567970
  • Filename
    567970