A 30 MHz FASTBUS transient digitizer data compactor using CMOS gate arrays

Author

Daviel, A.

Author_Institution

TRIUMF, Vancouver, BC, Canada

fYear

1992

fDate

25-31 Oct 1992

Firstpage

347

Abstract

A 16-channel data compactor built at TRIUMF for the BNL787 experiment is described. The module is designed to compact data from a 16-channel 256-bin 500-MHz CCD (charge coupled device) transient digitizer. Each channel accepts 8-bit digitized data from a CCD module, performs pedestal subtraction, and spike and zero suppression, and formats the data together with channel identifiers into 32-bit words for readout by FASTBUS. Data compaction is performed on-the-fly at a 30 MHz rate, with a 600-ns initial delay. Data for all channels may be read out in one FASTBUS block transfer operation. The module incorporates a fully featured FASTBUS slave interface built using a CMOS gate array (the PCL) and two bipolar gate arrays (ADIs)

Keywords

CCD image sensors; CMOS integrated circuits; analogue-digital conversion; logic arrays; nuclear electronics; 16-channel data compactor; 30 MHz; 32-bit words; 500 MHz; 600 ns; 8-bit digitized data; ADIs; BNL787 experiment; CCD; CMOS gate arrays; FASTBUS slave interface; FASTBUS transient digitizer data compactor; PCL; TRIUMF; bipolar gate arrays; block transfer operation; channel identifiers; charge coupled device; pedestal subtraction; spike; zero suppression; Background noise; Charge coupled devices; Clocks; Compaction; Councils; Delay; Fastbus; Field programmable gate arrays; Programmable logic arrays; Prototypes;

fLanguage

English

Publisher

ieee

Conference_Titel

Nuclear Science Symposium and Medical Imaging Conference, 1992., Conference Record of the 1992 IEEE

Conference_Location

Orlando, FL

Print_ISBN

0-7803-0884-0

Type

conf

DOI

10.1109/NSSMIC.1992.301251

Filename

301251