Fine-grain Reconfigurable Functional Unit for embedded processors

In standard word-oriented microprocessors, the processing of short data decreases the computation performance. In order to overcome this issue various methods based on reconfigurable architectures have been presented in the literature [1] [2] [3]. These structures are normally composed by an array of elementary reconfigurable cells. A common solution for elementary reconfigurable cells realization is based on Look-Up Tables (LUTs). In [4] [5] the authors proposed a new Reconfigurable Functional Unit (RFU) based on full adders and reprogrammable interconnects named ADAPTO. The final aim is to obtain a new structure that requires less silicon area and power, being ever faster than the “traditional” solutions. In this paper we present the main characteristics of the proposed structure evaluating its performance (in terms of speed-up and complexity) when integrated in an embedded processor.