Development of digital readout buffer schemes for silicon strip detectors at SDC

Summary form only. A 64-channel chip has been fabricated on a nonrad-hard CMOS 1.5 μ process. This chip consists of an event driven level 1 buffer for storing data from a beam crossing while its level 1 trigger decision is being made. Once the level 1 trigger decision has been made, the data are compressed into channel-encoded addresses and serially transmitted out of the chip. This chip also includes a separate module to determine at every beam crossing whether there is a single hit or a pair of hits or multiple hits on the 64 inputs. This information could be used for a level one trigger decision. The main aim of this chip is to understand the steps involved in designing a chip for silicon strip detectors at SDC and to test the event driven readout scheme