Testing fast ADC´s at sample rates between 20 and 140 MSPS

The performance of high-speed analog-to-digital converters (ADCs) suitable for use at the Superconducting Super Collider and the Large Hadron Collider has been tested. A test bench has been built to evaluate the performance of ADCs in the range of sampling rates from 20 to 240 megasamples per second (MSPS), thus permitting tests of devices under identical conditions and with identical parameter definitions. For each device, a large number of parameters have been measured, such as number of effective bits, noise level, aperture jitter, integral and differential nonlinearity, analog bandwidth, and total harmonic distortion. The authors describe some of the lessons learned from this test program and present results on a range of eight and ten bit devices