DocumentCode
1929744
Title
Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter
Author
Braunstein, Cécile ; Encrenaz, Emmanuelle
Author_Institution
Univ. Pierre et Marie Curie, Paris
fYear
2006
fDate
14-16 June 2006
Firstpage
103
Lastpage
109
Abstract
This work studies the relations between pipeline architectures and their specification expressed in CTL. We propose a method to build pipeline structures incrementally from a simple one (already verified) to a more complex one. Moreover, we show how each increment can be integrated in a CTL specification. We define increments to model treatment delay and treatment abortion of a pipeline flow, and we formalize the composition of the different increments. In order to represent the increments added to an architecture, we derive a set of CTL formulae transformations. Finally we model a control flow of a protocol converter by composition of these increments. We show how CTL properties of the complex architecture are built by applying automatic transformations on the set of CTL properties of the simplest architecture
Keywords
formal specification; pipeline processing; program verification; protocols; temporal logic; CTL specification; incremental design; pipelined protocol converter; treatment abortion; treatment delay; verification process; Abortion; Automatic control; Communication system control; Delay; Logic; Microprocessors; Network-on-a-chip; Pipelines; Process design; Protocols;
fLanguage
English
Publisher
ieee
Conference_Titel
Rapid System Prototyping, 2006. Seventeenth IEEE International Workshop on
Conference_Location
Chania, Crete
ISSN
1074-6005
Print_ISBN
0-7695-2580-6
Type
conf
DOI
10.1109/RSP.2006.19
Filename
1630757
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