An FPGA-Based Neural Network Digital Channel Equalizer

Author

Weng, Wan-de ; Lin, Rui-chang

Author_Institution

Nat. Yunlin Univ. of Sci. & Technol., Nantou

Volume

4

fYear

2007

fDate

19-22 Aug. 2007

Firstpage

1903

Lastpage

1908

Abstract

The hardware design of an SCFNN equalizer is presented in this paper. The system is implemented using Verilog hardware description language and has been verified with ALTERA Quartus II. The original equations in the algorithms have been partly rewritten to simplify the hardware design. It has been observed that several multiplications sharing the common operands are performed serially. By using multiplexers and de-multiplexers to replace the multipliers, we have successfully achieved about 30% savings on the hardware cost.

Keywords

equalisers; field programmable gate arrays; hardware description languages; multiplexing equipment; neural nets; FPGA-based neural network; SCFNN equalizer; Verilog hardware description language; de-multiplexers; digital channel equalizer; Bit error rate; Computational modeling; Costs; Equalizers; Equations; Field programmable gate arrays; Finite impulse response filter; Hardware; Neural networks; Nonlinear distortion; Channel equalizer; Fuzzy logic; Nural network; SCFNN;

fLanguage

English

Publisher

ieee

Conference_Titel

Machine Learning and Cybernetics, 2007 International Conference on

Conference_Location

Hong Kong

Print_ISBN

978-1-4244-0973-0

Electronic_ISBN

978-1-4244-0973-0

Type

conf

DOI

10.1109/ICMLC.2007.4370459

Filename

4370459