Performance consideration of an AC coupled gate drive circuit with forward bias for normally-on SiC JFETs

In this paper, an ac coupled driving circuit for normally-on Silicon Carbide (SiC) Junction Field Effect Transistors (JFETs) is proposed, utilizing forward bias during conduction state. Such driving circuits constitute the basic structure of a grid connected, 5kW photovoltaic (PV) inverter. The prototype is investigated in terms of efficiency, considering both conduction and switching losses and the advantages over a conventional zero biased gate drive are recorded. The adequacy of the particular circuit to efficiently drive a normally-off SiC JFET is also investigated. Simulation studies are carried out by developing new depletion mode (DM) as well as enhancement mode (EM) vertical trench (VT) SiC JFET models in Pspice model editor. The promising theoretical and simulation results are validated via experimental testing in a double pulse tester (DPT). Both DM and EM power devices are tested in a bridge leg configuration and their performance is evaluated, having as a reference point the operational characteristics of a conventional Silicon (Si) based IGBT power switch. Ultimately, a reduction of over 18% in conduction losses is obtained through forward biasing a DM SiC JFET, while switching losses less than 500 μJ are achieved over one switching cycle when operating at 600 V, 20 A.