Efficient FPGA implementation of a High throughput systolic array QR-decomposition algorithm

Due to the Multiple Input Multiple Output technology, applied in wireless communication, where a transceiver has to deal with multidimensional channels, the QR-decomposition is an often used preprocessing algorithm, especially for the design of iterative tree search detection algorithms. In this paper we introduce an efficient FPGA implementation of a QR-decomposition algorithm, which is designed for a MIMO detector developed in view of the Long Term Evolution (LTE). The proposed architecture is based on a line-by-line systolic array structure and reaches the peak matrix throughput, which is required to achieve the defined LTE peak data rate of a 2 × 2 MIMO constellation using a 20 MHz transmission bandwidth. In this paper we describe the architecture and FPGA implementation of the algorithm in detail and show the performance results of a Xilinx Virtex IV realization.