On the convergence of joint channel and mismatch estimation for time-interleaved data converters

Mostly digital architectures for communication transceivers rely on the use of accurate analog-to-digital converters (ADCs), which becomes a bottleneck in scaling to multi-Gigabit speeds. A promising workaround is to employ slower, power-efficient sub-ADCs in a time-interleaved ADC (TI-ADC) architecture. While mismatch between sub-ADCs can lead to performance floors, recent work shows that this can be mitigated using joint channel and mismatch compensation algorithms. In this paper, we investigate the scalability and convergence of a recently proposed iterative channel and mismatch estimation algorithm, and derive rules of thumb relating the required length of training to the number of sub-ADCs.