Low-power state assignment for asynchronous finite state machines

Author

Shieh, Ming-Der ; Ju, Wann-Shyang ; Sheu, Ming-hwa

Author_Institution

Dept. of Electron. Eng., Nat. Yunlin Inst. of Technol., Taiwan

Volume

3

fYear

1996

fDate

18-21 Aug 1996

Firstpage

1325

Abstract

In this paper a precise model for calculating the steady state probabilities and state transition probabilities of asynchronous finite state machines (AFSMs) is presented. Based on this model and the derived weighted adjacency diagram, an efficient unicode race-free state assignment technique is proposed to minimize the average switching activity of state variables, thus to potentially reduce the average power dissipation in AFSMs. Experimental results show that the proposed algorithm can achieve less switching activity of state variables in comparison with existing unicode state assignment techniques for AFSMs

Keywords

asynchronous circuits; asynchronous sequential logic; finite state machines; sequential circuits; state assignment; algorithm; asynchronous finite state machine; asynchronous sequential logic circuit; low-power state assignment; model; power dissipation; state transition probability; steady state probability; switching activity; unicode race-free technique; weighted adjacency diagram; Automata; Clocks; Electronic mail; Power dissipation; Probability; Sequential circuits; Steady-state; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1996., IEEE 39th Midwest symposium on

Conference_Location

Ames, IA

Print_ISBN

0-7803-3636-4

Type

conf

DOI

10.1109/MWSCAS.1996.593176

Filename

593176