DocumentCode :
1931486
Title :
Reconfigurable parallel computing
Author :
Tutsch, Dietmar
Author_Institution :
Autom. & Comput. Sci., Univ. of Wuppertal, Wuppertal, Germany
fYear :
2010
fDate :
28-30 Oct. 2010
Firstpage :
5
Lastpage :
5
Abstract :
Summary form only given. The dynamic reconfiguration of hardware stands for the change of hardware while the system is operating. Its benefit is the adaption to different computing requirements. For instance, an improved use of communication networks can be achieved: Many networks reveal the characteristic that connections between specific communication partners show a smaller latency than others. These localities (connections with a small latency) can be used for those communication partners who communicate heavily with each other. If several applications run in parallel on the system and a part of applications change, this can implicate that after the change, new partners with heavy communication cannot use a connection of small latency. Then, a dynamic reconfiguration of the network can help.
Keywords :
multiprocessing systems; network routing; parallel processing; reconfigurable architectures; system-on-chip; hardware operating system; multiprocessor system-on-chip architecture; network architecture; parallel system; reconfigurable parallel computing; reconfiguration management; routing strategies; spatial traffic distribution; switching strategies; Automation; Computational modeling; Computer architecture; Computer science; Context; Hardware; Routing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Parallel Distributed and Grid Computing (PDGC), 2010 1st International Conference on
Conference_Location :
Solan
Print_ISBN :
978-1-4244-7675-6
Type :
conf
DOI :
10.1109/PDGC.2010.5679961
Filename :
5679961
Link To Document :
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