Large Dynamic Range Accurate Digitally Programmable Delay Line with 250-ps Resolution

Author

Li, Jiaqi ; Zheng, Zhe ; Liu, Min ; Wu, Siliang

Author_Institution

Dept. of Electron. Eng., Beijing Inst. of Technol.

Volume

1

fYear

2006

fDate

16-20 2006

Abstract

This paper presents a design of large dynamic range accurate digitally programmable delay line with 250-ps resolution on a single field programmable gate array (FPGA) chip. This design adopts time-to-digital conversion (TDC) technology, counter-based delay technology and small range digitally programmable delay line technology. When working with an oscillator with frequency accuracy of plusmn1 ppm, and when the delay range is within 0~0.1 ms, the delay accuracy of our design can reach plusmn350 ps

Keywords

delay lines; field programmable gate arrays; network synthesis; oscillators; 0 to 0.1 ms; FPGA chip; counter-based delay technology; large dynamic range accurate digitally programmable delay line; oscillator; single field programmable gate array chip; small range digitally programmable delay line technology; time-to-digital conversion technology; Clocks; Counting circuits; Delay effects; Delay lines; Dynamic range; Field programmable gate arrays; Frequency; Pulse circuits; Pulse measurements; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing, 2006 8th International Conference on

Conference_Location

Beijing

Print_ISBN

0-7803-9736-3

Electronic_ISBN

0-7803-9736-3

Type

conf

DOI

10.1109/ICOSP.2006.345484

Filename

4128909