DocumentCode :
1931755
Title :
Review on the high temperature warpage measurement using shadow moiré
Author :
Um, YongGoo ; Khim, JinYoung
Author_Institution :
Amkor Technol. Korea, Seoul, South Korea
fYear :
2010
fDate :
24-26 Aug. 2010
Firstpage :
1
Lastpage :
4
Abstract :
Recently, the members of Jedec committee tried to publish new warpage spec criteria for high temperature to reduce SMT quality issue (open/short) during the reflow on the purpose of the development and the qualification of a component. In order to verify the repeatability and reliability of warpage data with shadow moire, the study on high temperature warpage measurement was performed. From this study, it was found that the warpage could be changed by various measurement parameters such as ramp rate, sample preparation, setup condition even though the JEDEC (JESD22B112) and JEITA (ED-7306) specification was fully followed. Finally, in this paper, we tried to suggest the best known method considering key experimental factors which could affect the warpage in view point of high temperature warpage measurement.
Keywords :
integrated circuit packaging; integrated circuit testing; surface mount technology; temperature; JEDEC committee; JEITA ED-7306 specification; JESD22B112 specification; SMT quality issue; high temperature warpage measurement; shadow moire; warpage specification criteria; Current measurement; Heating; Semiconductor device measurement; Semiconductor device modeling; Temperature; Temperature measurement; Thermal stresses;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
CPMT Symposium Japan, 2010 IEEE
Conference_Location :
Tokyo
Print_ISBN :
978-1-4244-7593-3
Type :
conf
DOI :
10.1109/CPMTSYMPJ.2010.5679977
Filename :
5679977
Link To Document :
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