Design and Implementation of Efficient On-Chip Crosstalk Avoidance CODECs Using Fibonacci Numeral System

Integrated Circuit(IC) design has seen a revolutionary progress in the past two decades with shrinking sizes of VLSI fabrication processes. This has an advantage of fabricating millions of transistors in a single chip IC. On the other hand it also creates many challenges in Deep Sub-Micron (DSM) technologies. One of the greatest challenges in DSM designs is inter-wire cross talk, which becomes significant due to coupling capacitance between wires. The effect of inter wire cross talk is that it greatly limits speed and increases power consumption of IC. This paper focuses on design and implementation of an efficient CODEC which uses Forbidden Pattern Free (FPF), Fibonacci based Number System (FNS) for bus encoding. Our approach of CODEC design greatly increases the speed (approximately greater than 2.5 times) and decreases the power consumption with the best existing technologies.