Title :
Development of multi-stack process on wafer-on-wafer (WOW)
Author :
Fujimoto, Koji ; Maeda, Nobuhide ; Kitada, Hideki ; Kim, Youngsuk ; Kawai, Akihito ; Arai, Kazuhisa ; Nakamura, Tomoji ; Suzuki, Kousuke ; Ohba, Takayuki
Author_Institution :
Univ. of Tokyo, Tokyo, Japan
Abstract :
The multi-stack process on wafer-on-wafer (WOW) has been developed. In order to realize the multi-stacked wafer with ultra thinned wafer of less than 10 μm with adhesive polymer, several processes have been optimized. The wafer thickness after back-grinding was controlled within the total thickness variation (TTV) of 1.2 μm on wafer-level of 8 inch. For the side wall of though silicon vias (TSV), SiN film with low deposition temperature of 150°C has been developed and applied for TSV process without degradation for electrical characteristics. The uniformity of Cu electro-plating has been improved that the overburdened Cu from the surface was decreased from 13.3 μm to 0.7 μm by optimizing plating solution. The CMP process following Cu electro-plating has been customized for the high rate of 5 μm/min. Finally, the stacked wafer has been evaluated for thermal cycle test (TCT) of 100 cycles with -65 to 150°C. The result showed that there was no degradation for packaging process.
Keywords :
chemical mechanical polishing; copper; electroplating; grinding; integrated circuit interconnections; integrated circuit manufacture; silicon compounds; three-dimensional integrated circuits; wafer bonding; Cu; SiN; adhesive polymer; chemical mechanical polishing; electroplating; multi-stack process; temperature -65 degC to 150 degC; thermal cycle test; though silicon vias; total thickness variation; ultra thinned wafer; wafer-on-wafer; Bonding; Copper; Silicon; Silicon compounds; Temperature measurement; Through-silicon vias;
Conference_Titel :
CPMT Symposium Japan, 2010 IEEE
Conference_Location :
Tokyo
Print_ISBN :
978-1-4244-7593-3
DOI :
10.1109/CPMTSYMPJ.2010.5679983
