A novel approach to real-time verification of transport system design using FPGA based emulator

This paper discusses a new approach to efficient system design verification that uses an FPGA based real-time emulator. The architecture of a real-time emulator suitable for high-speed digital transmission system emulation and an experimental system are described. The proposed system consists of an emulation engine using the custom designed multi-chip module FPGA called PROTEUS-MCM, a program control unit, and a physical interface. The system can be used not only for real-time emulation of high-speed transmission systems, but also as initial systems for actual communication networks