Hierarchical partitioning in a rapid prototyping environment

Rapid prototyping is a well accepted method in microsystems technology. During early design phases a design can be checked against its requirements and, using FPGAs, we are able to easily implement changes and correct faults. The emulation board of the design called MCEMS (Methodology for the design of Embedded Microelectronic Systems), is assembled by FPGAs. To map an application specific embedded controller to this emulation board, the netlist has to be partitioned. None of the existing partitioning strategies are suitable for this system. In this paper we present a hierarchical partitioning approach that satisfies the requirements of this special application