DocumentCode
1932490
Title
The effects of gate and drain biases on the stability of low temperature poly-Si TFTs
Author
Young, N.D. ; Gill, A
Author_Institution
Philips Research Laboratories, Redhill, Surrey, UK.
fYear
1990
fDate
10-13 Sept. 1990
Firstpage
303
Lastpage
306
Abstract
Instabilities in low temperature poly-Si TFTs are shown to be due to the tunnelling of electrons into taps in the gate oxide, and to hot carrier induced interface acceptor state generation and trapping. Little evidence is seen for the creation of states in the poly-Si in the manner which has been reported for high temperature poly-Si TFTs. However, there is some evidence for the creation of mid gap acceptors and generation centres in our devices.
Keywords
Degradation; Electron mobility; Electron traps; Glass; Plasma immersion ion implantation; Plasma stability; Plasma temperature; Stress; Thermal stability; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1990. ESSDERC '90. 20th European
Conference_Location
Nottingham, England
Print_ISBN
0750300655
Type
conf
Filename
5436355
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