DocumentCode
1933120
Title
Jitter analysis of mixed PLL-DLL architecture in DRAM environment
Author
Sayfullah, Md
Author_Institution
Concept Eng., Qimonda AG, Munich, Germany
fYear
2009
fDate
25-27 June 2009
Firstpage
445
Lastpage
449
Abstract
This paper presents the application feasibility of mixed mode PLL-DLL in DRAM. Jitter analysis of mixed mode PLL-DLL in DRAM environment has been carried out. According to the jitter type, this model can be used as pure PLL or pure DLL or a mixed PLL-DLL. It is observed that mixed mode PLL-DLL architecture can combine the advantage from both PLL and DLL to reduce jitter in DRAM.
Keywords
DRAM chips; delay lock loops; jitter; phase locked loops; DRAM environment; delay locked loop; jitter analysis; mixed PLL-DLL architecture; phase locked loop; Circuit noise; Clocks; Delay; Frequency; Jitter; Low-frequency noise; Noise figure; Phase locked loops; Random access memory; Transfer functions; DLL; DRAM jitter; PLL; jitter transfer function; mixed PLL-DLL;
fLanguage
English
Publisher
ieee
Conference_Titel
Mixed Design of Integrated Circuits & Systems, 2009. MIXDES '09. MIXDES-16th International Conference
Conference_Location
Lodz
Print_ISBN
978-1-4244-4798-5
Electronic_ISBN
978-83-928756-1-1
Type
conf
Filename
5289485
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