DocumentCode
1933312
Title
High density 3D, CMOS circuits with ELO SOI technology
Author
Roos, Gerhard ; Hoefflinger, Bernd ; Zingg, Rene
Author_Institution
Institute for Microelectronics Stuttgart IMS, Allmandring 30a, 7000 Stuttgart 80, West Germany
fYear
1990
fDate
10-13 Sept. 1990
Firstpage
9
Lastpage
12
Abstract
A priori crystalline silicon-on-insulator-on-silicon structures were fabricated with 8 masks. With this three-dimensional CMOS technology, three high-quality transistor channels are stacked vertically. Dual-gate PMOS transistors on top of NMOS transistors deliver the same current for the same channel width. 3D CMOS test circuits have been built with a footprint of one third of their 2D bulk counterparts.
Keywords
CMOS logic circuits; CMOS process; CMOS technology; Circuit testing; Crystallization; MOS devices; MOSFETs; Measurement standards; Silicon; Thin film transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1990. ESSDERC '90. 20th European
Conference_Location
Nottingham, England
Print_ISBN
0750300655
Type
conf
Filename
5436392
Link To Document