DocumentCode
1933686
Title
Reactive tiling
Author
Srinivas, Jithendra ; Wei Ding ; Kandemir, Mahmut
fYear
2015
fDate
7-11 Feb. 2015
Firstpage
91
Lastpage
102
Abstract
To fully exploit the power of emerging multicore architectures, managing shared resources (i.e., caches) across applications and over time is critical. However, to our knowledge, most prior efforts view this problem from the OS/hardware side, and do not consider whether applications themselves can also participate in this process of managing shared resources. In this paper, we show how an application can react to OS/hardware-based resource management decisions by adapting itself (called reactive application), with the goal of maximizing the utilization of the shared resources allocated to it. Specifically, we present a framework that can generate code for adaptive (reactive) tiling, and propose an execution model in which a reactive application can react to the modulations in its cache space allocations to prevent its performance from degrading. One can expect two potential benefits from this approach. First, matching tile size to available cache capacity dynamically (during execution) improves performance of the target application. Second and equally important, better utilization of shared cache space reduces pressure on other applications (co-runners) that execute concurrently with the target application. Our experimental results show that the proposed scheme improves the performance of applications (over the best static tiles) by 8.4%, on average, when using synthetic cache allocations. Further with dynamic cache allocations determined by the utility-based cache partitioning (a state-of-the-art cache partitioning scheme), it improves performance of a set of eleven HPC applications by 11.3%.
Keywords
cache storage; multiprocessing systems; operating systems (computers); parallel architectures; resource allocation; HPC applications; OS-hardware-based resource management decisions; cache capacity; cache space allocations; dynamic cache allocations; multicore architectures; reactive tiling; shared cache space; shared resource management; synthetic cache allocations; utility-based cache partitioning; Dynamic scheduling; Hardware; Modulation; Optimization; Resource management; Runtime; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Code Generation and Optimization (CGO), 2015 IEEE/ACM International Symposium on
Conference_Location
San Francisco, CA
Type
conf
DOI
10.1109/CGO.2015.7054190
Filename
7054190
Link To Document