A behavioural model for sigma delta fractional PLL

This paper presents an accurate high level model for the design of sigma-delta fractional Phase locked loop (PLL) architectures. High level models provide simulation speedups of about two orders of magnitude when compared to transistor level simulation. When compared to other models present in the literature the proposed model has the advantage of having the frequency instead of phase as the output of the VCO. This approach greatly simplifies the implementation of the PLL blocks and results in an increase of the overall model performance. Several nonlinear phenomenons such as cycle slipping, spurious signals and phase noise are also accurately modelled.