Hardware realization of the modular exponentiation operation in cryptographic systems based on binary and multivalued logic

This paper presents several architectures of circuits destined to the realization of the modular exponentiation operation c = (m^e) mod n, which is the basic and most time-consuming operation in the cryptographic algorithm RSA. Then, a modification of one of the presented architectures is shown, which was carried out to enable the realization of the exponentiation circuit with current-mode digital gates. Such realization radically increases the cryptographic system´s level of immunity to PAA attacks and to attacks by the analysis of electromagnetic field changes.