Physical design of dual-core system-on-chip

To meet the aggressive time-to-market requirement, fast prototyping methodology is employed to shorten design cycle. To satisfy stringent path timing, a novel diagonal floorplan is integrated to enhance the data sharing between different cores in system on chip. In this paper, physical design of MediaSOC3221A shows how system on chip is planed and unified, with balanced clock trees and effective power distribution. As a result, the physical design of a dual-core chip is accomplished in only five days with good performance.