Title :
Physical design of dual-core system-on-chip
Author :
Teng, Zhaowei ; Liu, Peng ; Lai, Liya
Author_Institution :
Dept. of Inf. Sci. & Electron. Eng., Zhejiang Univ., Hangzhou, China
Abstract :
To meet the aggressive time-to-market requirement, fast prototyping methodology is employed to shorten design cycle. To satisfy stringent path timing, a novel diagonal floorplan is integrated to enhance the data sharing between different cores in system on chip. In this paper, physical design of MediaSOC3221A shows how system on chip is planed and unified, with balanced clock trees and effective power distribution. As a result, the physical design of a dual-core chip is accomplished in only five days with good performance.
Keywords :
integrated circuit design; system-on-chip; time to market; MediaSOC3221A design; balanced clock trees; data sharing; diagonal floorplan; dual-core system-on-chip design; fast prototyping methodology; power distribution; stringent path timing; time-to-market requirement; Clocks; Delay; Logic design; Power distribution; Prototypes; Silicon; System-on-a-chip; Timing; Uncertainty; Wire;
Conference_Titel :
VLSI Design and Video Technology, 2005. Proceedings of 2005 IEEE International Workshop on
Print_ISBN :
0-7803-9005-9
DOI :
10.1109/IWVDVT.2005.1504458
