A new 0·5μm2 DRAM cell with internal charge gain investigated by 2D transient device simulation

The Vertically Integrated Gain (VIG) cell is a new DRAM structure for 64/256 Mbit ORAMs. By using a trench structure and 0.25 μm design rules a cell size of 0.55μm² is attainable. The cell function bases on merging 2 bipolar junction transistors (BJT), 1 junction field effect transistor (JFET) and 2 capacitors. 20 transient device simulation is used to investigate the electrical behaviour of the VIG cell. A high read out signal, 2 control lines, operation voltages between 0 and 5 volts only and the capability to maintain the stored information during read operation are the main features of the proposed DRAM cell.