Hot-carrier experiments on scaled NMOS transistors

Hot-carrier reliability limits the operation voltage for downscaled NMOS transistors. Transistors made according to Quasi Constant Voltage Scaling with design rules between 2.5 ¿m and 0.25 ¿m are tested for reliability and performance. We show that this scaling is in accordance with hot-carrier reliability. The maximal output power (per unit width) is independent of the design rule, but a factor of two more output is possible for LDD transistors. The gate delay appears to be proportional to the design rule, independent of the drain structure.