GaAs multiplexer chip for ATM switching

Author

Jakobsen, J.

Author_Institution

Tele Danmark Jydsk Telefon R&D, Tranbjerg, Denmark

fYear

1995

fDate

Oct. 29 1995-Nov. 1 1995

Firstpage

35

Lastpage

38

Abstract

This paper describes the design of a GaAs multiplexer chip which can be used for the implementation of an ATM switch fabric. In order to achieve low power, a self-timed FIFO with automatic power off was designed. For high speed and low power a static flip-flop with push-pull output stage was also designed. The chip works at 1.15 GHz, corresponding to a throughput of 10 Gb/s. This is achieved at a power consumption of 1.2 W.

Keywords

B-ISDN; III-V semiconductors; MESFET integrated circuits; asynchronous transfer mode; direct coupled FET logic; field effect logic circuits; field effect transistor switches; flip-flops; gallium arsenide; multiplexing equipment; timing; 0.8 micron; 1.15 GHz; 1.2 W; 10 Gbit/s; ATM switching; DCFL; GaAs; MESFET process; SBFL; SDCFL; automatic poweroff; high speed operation; low power operation; multiplexer chip; push-pull output stage; self-timed FIFO; static flip-flop; Asynchronous transfer mode; FETs; Fabrics; Flip-flops; Gallium arsenide; Logic design; Multiplexing; Research and development; Switches; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1995. Technical Digest 1995., 17th Annual IEEE

Conference_Location

San Diego, CA, USA

Print_ISBN

0-7803-2966-X

Type

conf

DOI

10.1109/GAAS.1995.528955

Filename

528955