An ECL implementation of the Motorola 88000

Author

Lewine, Donald A. ; Guyer, James ; Baxter, Bill ; Moriondo, Chris

Author_Institution

Data Gen. Corp., Westboro, MA, USA

fYear

1989

fDate

Feb. 27 1989-March 3 1989

Firstpage

27

Lastpage

31

Abstract

The high performance of the Motorola 88000 architecture, which uses ECL (emitter-coupled logic) technology, is discussed. The ECL 88000 is implemented using Motorola´s MCA4 technology. This provides about 50000 ECL gates in a macro cell array structure. The ECL 88000 uses both standard and custom macros within the array. The chip is packaged in a TAB (tape automated bonding) package and dissipates about 40 W. The ECL 88000 can be cooled with forced ambient room air. The cache and associated tag stores are implemented with discrete RAMs. The ECL 88000 is 100% object code-compatible with the original CMOS implementation. Software can be transported freely between the two machines. The basic Harvard architecture of the original implementation is maintained.<>

Keywords

CMOS integrated circuits; emitter-coupled logic; lead bonding; microprocessor chips; CMOS implementation; ECL implementation; Harvard architecture; MCA4 technology; Motorola 88000; cache; macro cell array structure; object code-compatible; tape automated bonding; CMOS logic circuits; CMOS process; Cache memory; Cache storage; Memory management; Microprocessors; Packaging; Programming profession; Registers; System buses;

fLanguage

English

Publisher

ieee

Conference_Titel

COMPCON Spring '89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, Digest of Papers.

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-1909-0

Type

conf

DOI

10.1109/CMPCON.1989.301898

Filename

301898