Design concept and implementation of mu ITRON specification for the H8/500 series

Author

Takeyama, Hiroshi ; Shimizu, Tsuyoshi ; Kobayakawa, Manabu

Author_Institution

Hitachi Ltd., Kodaira, Japan

fYear

1989

fDate

Feb. 27 1989-March 3 1989

Firstpage

48

Lastpage

53

Abstract

A description is given of HI8, a compact operating system (OS) based on the mu ITRON specification that has been developed for the H8/500 series of single-chip microcomputers. HI8 fully implements level three of the mu ITRON specification. Concerning two critical parameters of real-time operation, HI8 has been confirmed to have a maximum interrupt-masked time of 15.0 mu s and maximum task dispatching time of 24.0 mu s. The OS object code has been compressed to a size of 1.9 kb to 4.7 kb, leaving ample space for application programs to operate in the on-chip ROM (32 kb) and RAM (1 kb) of the H8/532. It is anticipated that real-time operating systems conforming to the mu ITRON specification will come into use in the single-chip application field. Current plans call for HI8 to be expanded to support levels four and five of the mu ITRON specification.<>

Keywords

microprocessor chips; operating systems (computers); 15 mus; 24 mus; H8/500 series; HI8; Hitachi; RAM; application programs; compact operating system; design concept; implementation; mu ITRON specification; on-chip ROM; real-time operation; single-chip microcomputers; Application software; Communication system control; Microcomputers; Operating systems; Pins; Prefetching; Pulse width modulation; Read only memory; Resumes; Software standards;

fLanguage

English

Publisher

ieee

Conference_Titel

COMPCON Spring '89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, Digest of Papers.

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-1909-0

Type

conf

DOI

10.1109/CMPCON.1989.301902

Filename

301902