Title :
Design of a 60 GHz LNA with 20 dB gain and 12 GHz BW in 65 nm LP CMOS
Author :
Chai, Yuan ; Li, Lianming ; Cui, Tiejun
Author_Institution :
Sch. of Inf. Sci. & Eng., Southeast Univ., Nanjing, China
Abstract :
A 60 GHz three-stages broadband Low Noise Amplifier (LNA) is designed in a 65 nm LP CMOS process. By controlling the reflection coefficients of components within the targeted frequency band, the trade-off among gain, noise figure (NF) and power consumption is realized. Simulation results show that the transducer gain is greater than 20 dB, and the noise figure is less than 6 dB, with a power consumption of 34.22 mW from a 1.2 V supply. The in-band ripple is less than 1 dB from 57 GHz to 66 GHz, and the 3-dB bandwidth is from 55 GHz to 67 GHz.
Keywords :
CMOS analogue integrated circuits; low noise amplifiers; millimetre wave amplifiers; power consumption; LNA; LP CMOS; bandwidth 12 GHz; frequency 55 GHz to 37 GHz; frequency 60 GHz; gain 20 dB; gain 3 dB; power 34.22 mW; size 65 nm; voltage 1.2 V; Bandwidth; CMOS integrated circuits; Gain; Noise; Noise figure; Transistors; 60 GHz; CMOS; Low noise amplifier (LNA); mm-wave;
Conference_Titel :
Microwave Workshop Series on Millimeter Wave Wireless Technology and Applications (IMWS), 2012 IEEE MTT-S International
Conference_Location :
Nanjing
Print_ISBN :
978-1-4673-0901-1
Electronic_ISBN :
978-1-4673-0903-5
DOI :
10.1109/IMWS2.2012.6338232
