DocumentCode
1935145
Title
32 taps digitally controlled buffered potentiometer
Author
Stanescu, Cornel ; Tache, Adrian ; Iacob, Radu
Author_Institution
Essex Com. Ltd., Bucharest, Romania
Volume
2
fYear
2001
fDate
37165
Firstpage
535
Abstract
The paper presents a 32-tap digitally controlled buffered potentiometer designed in a 0.8 μm CMOS process. An up/down counter determines which tap is connected to the output. Output settings are stored in nonvolatile memory. A rail-to-rail op amp is used as unity-gain buffer at the output in order to eliminate the errors given by the load
Keywords
CMOS integrated circuits; buffer circuits; counting circuits; integrated circuit design; integrated circuit measurement; operational amplifiers; potentiometers; random-access storage; 0.8 micron; CMOS process; digitally controlled buffered potentiometer; load errors; multi-tap digitally controlled buffered potentiometer; nonvolatile memory; output setting storage; rail-to-rail op amp; tap output connection; unity-gain buffer; up/down counter; CMOS process; Counting circuits; Decoding; Digital control; EPROM; Operational amplifiers; Potentiometers; Resistors; Switches; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Conference, 2001. CAS 2001 Proceedings. International
Conference_Location
Sinaia
Print_ISBN
0-7803-6666-2
Type
conf
DOI
10.1109/SMICND.2001.967523
Filename
967523
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