Improvements of SEU tolerance by spatial redundancy in digital circuits

Together with development of semiconductor technology the digital circuits are more and more susceptible to Single Event Upsets that changes information stored in memory components in non-predictible way. This is particularly important for circuits operating in radioactive environment but becomes also an important factor limiting reliability for circuits operating at normal conditions. The countermeasure is a redundancy in circuit that allows to detect and correct errors caused by radiation. Unfortunately CAD software provides very limited support to simulate the consequences of SEU and automatically include required redundancy in the FPGA project. Moreover, optimization procedures remove redundant parts and special effort must be made to prevent that. The paper presents a software environment to process VHDL description of the circuit and automatically generate the redundant blocks together with voting circuits. The generated redundancy uses Triple Module Redundancy (TMR) scheme. It also supports the VHDL simulation with SEUs in order to enable identification of the most sensitive components. Since the TMR is costly, the designer can indicate which parts of the circuit should be replicated basing on the results of simulation.