Performance and Reliability of Sub-micron PMOS Devices Formed by Implantation into Silicide

Dopant implantation into TiSi12 and low temperature annealing have been used to fabricate submicron PMOS transistors. Spreading resistance measurements show that very shallow junctions can be formed by the technique. Dopant penetration through the silicide during implantation is found to occur in some cases. Electrical measurement show that good quality devices can be formed, whilst electrically stressing the devices indicates that no enhanced device degradation is observed as compared to conventionally formed PMOS devices.