Simulated annealing based delay centric VLSI circuit partitioning

Two way partitioning of a circuit represented as a graph, has been carried out using simulated annealing in the present work. The problem is solved in such a way that delay between the partitions is minimum. The parameters used in the annealing process are initial temperature, cooling rate, and threshold. The influence of these parameters on the delay between the partitions is evaluated. The method is tested on a test case with 102 components connected by 103 nets. Substantial improvement in delay has been obtained over the initial circuit delay justifying the effectiveness of proposed method.