Pedestal Collector in Advanced Bipolar Technology for Improved Speed Power Performance

A double poly-Si self-aligning bipolar process employing 1, ¿m lithography has been developed for very high speed/low power circuit applications. Shallow base-emitter profiles were obtained by combining low energy boron implantation and rapid thermal annealing for the emitter drive-in. Cut-off frequencies of 14 GHz at VBC = -1 V, ECL gate delay times of 43 ps and minimum power delay products of 30 fj were achieved with conventional epitaxial collector configurations. Further improvements in cut-off frequency up to 18 GHz, gate delay and minimum power delay product as low as 36 ps and 23 fJ, respectively, were attained by an additional implantation of doubly ionized phosphorus into the active device area forming a so-called pedestal collector.