Title :
Integration of high-k gate stack systems into planar CMOS process flows
Author :
Huff, H.R. ; Agarwal, A. ; Kim, Y. ; Perrymore, L. ; Riley, D. ; Barnett, J. ; Sparks, C. ; Freiler, M. ; Gebara, G. ; Bowers, B. ; Chen, P.J. ; Lysaght, P. ; Nguyen, B. ; Lim, J.E. ; Lim, S. ; Bersuker, G. ; Zeitzoff, P. ; Brown, G.A. ; Young, C. ; Foran
Author_Institution :
Int. SEMATECH, Inc, Austin, TX, USA
Abstract :
We review several gate stack fabrication issues critical for robust, commercially viable tools, including assessment of possible fab contamination due to the higher-k gate dielectrics and the role of subsequent thermal procedures during, for example, source/drain anneals (including the importance of the oxygen partial pressure) to ensure their compatibility with conventional planar polysilicon CMOS transistor fabrication processes.
Keywords :
CMOS integrated circuits; annealing; dielectric thin films; integrated circuit metallisation; fab contamination; high-k gate dielectric; high-k gate stack fabrication; planar CMOS process flow; polysilicon CMOS transistor; thermal annealing; CMOS process; Delay; Electrodes; High K dielectric materials; High-K gate dielectrics; Leakage current; MOSFETs; Microelectronics; Random access memory; Silicon;
Conference_Titel :
Gate Insulator, 2001. IWGI 2001. Extended Abstracts of International Workshop on
Conference_Location :
Tokyo, Japan
Print_ISBN :
4-89114-021-6
DOI :
10.1109/IWGI.2001.967538
