The prospect of using thin oxides for silicon nanotransistors

Author

Alam, M. ; Weir, B. ; Silverman, P.

Author_Institution

Agere Syst., Murray Hill, NJ, USA

fYear

2001

fDate

1-2 Nov. 2001

Firstpage

30

Lastpage

34

Abstract

We scale down transistors in each successive technology generation to increase circuit speed and to improve packing density. However, as scaling continues beyond the 0.1 /spl mu/m technology generation, concerns about three issues, reliability, leakage and mobility degradation, must be addressed. This paper summarizes the current understanding regarding these issues, and identifies areas on which device scaling research could focus.

Keywords

CMOS integrated circuits; MOSFET; carrier mobility; elemental semiconductors; integrated circuit layout; integrated circuit reliability; leakage currents; nanotechnology; semiconductor device reliability; silicon; 0.1 micron; CMOS technology; MOSFETs; SiO/sub 2/-Si; circuit speed; device scaling; leakage; mobility degradation; packing density; reliability; silicon nanotransistors; technology generation; technology scaling; thin oxides; transistor downscaling; Circuits; Degradation; Hot carriers; Human computer interaction; MOS devices; MOSFETs; Power dissipation; Silicon; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Gate Insulator, 2001. IWGI 2001. Extended Abstracts of International Workshop on

Conference_Location

Tokyo, Japan

Print_ISBN

4-89114-021-6

Type

conf

DOI

10.1109/IWGI.2001.967542

Filename

967542