DocumentCode
1935972
Title
Conflict graph based hardware transactional memory
Author
Zeng, Kun
Author_Institution
Nat. Lab. for Parallel & Distrib. Process., Nat. Univ. of Defense Technol., Changsha, China
Volume
5
fYear
2010
fDate
9-11 July 2010
Firstpage
496
Lastpage
501
Abstract
This paper proposes a novel transactional memory design: conflict graph based hardware transactional memory. It allows two conflicting transactions both to commit if they do not violate the condition of serializability. Simulation results show that conflict graph based hardware transactional memory outperforms the state-of-art transactional memory system.
Keywords
graph theory; parallel programming; shared memory systems; transaction processing; conflict graph; hardware transactional memory; serializability condition; Protocols; conflict detection; conflict graph; serializability; transactional memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Science and Information Technology (ICCSIT), 2010 3rd IEEE International Conference on
Conference_Location
Chengdu
Print_ISBN
978-1-4244-5537-9
Type
conf
DOI
10.1109/ICCSIT.2010.5563895
Filename
5563895
Link To Document