Title :
Towards hardware implementation of bzip2 data compression algorithm
Author :
Szecówka, Przemyslaw M. ; Mandrysz, Tomasz
Author_Institution :
Fac. of Microsyst. Electron. & Photonics, Wroclaw Univ. of Technol., Wroclaw, Poland
Abstract :
Digital architecture dedicated to bzip2 data compression algorithm is proposed. The full functionality of 3 steps of bzip2 - Burrows-Wheeler transform (BWT), Move to front and Huffman coding was achieved for data blocks of 64 hexadecimal characters. Series of logic devices - coders, finite state machines, was implemented in VHDL, verified and synthesized for FPGA. Implementation of Bitonic sort algorithm appeared to be the most difficult and critical part of the design.
Keywords :
Huffman codes; data compression; field programmable gate arrays; finite state machines; hardware description languages; sorting; transform coding; Bitonic sort algorithm; Burrows-Wheeler transform; FPGA; Huffman coding; VHDL; bzip2 data compression algorithm; digital architecture; finite state machine; hexadecimal character; logic device; Algorithm design and analysis; Automata; Data compression; Data structures; Field programmable gate arrays; Hardware; Huffman coding; Integrated circuit technology; Logic devices; Photonic integrated circuits; Burrows-Wheeler transform; FPGA; Huffman coding; VHDL; bzip2; data compression; hardware;
Conference_Titel :
Mixed Design of Integrated Circuits & Systems, 2009. MIXDES '09. MIXDES-16th International Conference
Conference_Location :
Lodz
Print_ISBN :
978-1-4244-4798-5
Electronic_ISBN :
978-83-928756-1-1
