A 8-b 250-MS/S track-and-hold circuit in 0.18-μM CMOS

Author

Chunming, Zhang ; Zhibiao, Shao ; Dong, Zhou

Author_Institution

Inst. of Microelectron., Xi´´an Jiaotong Univ., China

fYear

2005

fDate

28-30 May 2005

Firstpage

83

Lastpage

86

Abstract

This paper presents a novel design of a high-speed track-and-hold (T/H) circuit, featuring 8-b resolution up to 250 Ms/s and 100 MHz bandwidth. It is designed in a 0.18 μm CMOS process with a supply voltage of 1.8 Volt. The implemented input buffer allows a relatively large input range, 1 v-Vpp differential, and low harmonic distortion at the same time. A switched capacitor topology is used or the T/H circuit and amplifier is a folded cascode OTA with regulated cascode. In order to cancel the offset error between the inputs of an operational amplifier (OP-amp), a correlated double sampling (CDS) is used. The switches used are of transmission gate type. The circuit is supposed to work together with an embedded 250-Ms/s 150 mw 8-bit folding and interpolating CMOS ADC 0.18 μm. The track-and-hold consumes 7.7 mw.

Keywords

CMOS analogue integrated circuits; harmonic distortion; integrated circuit design; network topology; operational amplifiers; sample and hold circuits; switched capacitor networks; 0.18 mum; 1.8 V; 100 MHz; 150 mW; 7.7 mW; CMOS process; correlated double sampling; harmonic distortion; operational amplifier; supply voltage; switched capacitor topology; track-and-hold circuit; transmission gate type; Bandwidth; CMOS process; Circuit topology; Harmonic distortion; Operational amplifiers; Sampling methods; Switched capacitor circuits; Switches; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design and Video Technology, 2005. Proceedings of 2005 IEEE International Workshop on

Print_ISBN

0-7803-9005-9

Type

conf

DOI

10.1109/IWVDVT.2005.1504556

Filename

1504556