Low-power logic design based on gate driving way considering interconnections capacitances

Author

Brzozowski, Ireneusz ; Kos, Andrzej

Author_Institution

Dept. of Electron., AGH Univ. of Sci. & Technol., Cracow, Poland

fYear

2009

fDate

25-27 June 2009

Firstpage

450

Lastpage

455

Abstract

This paper presents design method of low-power integrated circuits based on information on primary inputs vectors changes, considering interconnections in real chip. The tested chip, which includes 32 digital circuits, was designed in CMOS AMS 0.35 mum technology. Taking advantage of gate driving way-the reason of a gate switching-two-level logic functions were synthesized for low-power. Previously developed design methods: proper choosing of a function cover, and 2-level circuit transformation into 3-level, have been modified. So now interconnection capacitance is evaluated and taken into consideration during logic synthesis. Additionally some post layout simulations were done for verification.

Keywords

CMOS integrated circuits; capacitance; integrated circuit interconnections; logic design; logic gates; low-power electronics; 2-level circuit transformation; CMOS AMS technology; digital circuits; function cover; gate driving way; gate switching; interconnection capacitance; interconnections capacitance; logic synthesis; low-power integrated circuit; low-power logic design; primary inputs vector; two-level logic function; CMOS digital integrated circuits; CMOS technology; Capacitance; Circuit testing; Design methodology; Digital circuits; Integrated circuit interconnections; Integrated circuit technology; Logic design; Logic functions; Low-power logic design; chip design; gate driving way; gate placement; interconnections;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits & Systems, 2009. MIXDES '09. MIXDES-16th International Conference

Conference_Location

Lodz

Print_ISBN

978-1-4244-4798-5

Electronic_ISBN

978-83-928756-1-1

Type

conf

Filename

5289622