Optimized design for high-speed parallel BCH encoder

Author

Jun, Zhang ; Zhi-Gong, Wing ; Qing-Sheng, Hu ; Jie, Xiao

Author_Institution

Inst. of RF & OE-IC, Southeast Univ., Nanjing, China

fYear

2005

fDate

28-30 May 2005

Firstpage

97

Lastpage

100

Abstract

A new design method for parallel BCH encoder is presented, which can eliminate the bottleneck in long BCH encoder. Based on serial LFSR architecture, a recursive formula which can deduce the parallel BCH encoder was first derived. The complexity and the delay of the critical paths of the circuit could be effectively decreased by using a tree-type structure, sharing sub-expression and limiting its maximum number, and balancing load technique. Finally, a parallel BCH (2184, 2040) encoder with 8-bit parallelism is realized in TSMC´s 0.18 μm CMOS technology for high-speed optical communication that can operate at 400 MHz and process data at the rate of 2.5 Gb/s.

Keywords

BCH codes; matrix algebra; parallel algorithms; shift registers; 0.18 mum; 2.5 Gbit/s; 400 MHz; 8 bit; CMOS technology; balancing load technique; design optimization; high-speed optical communication; high-speed parallel BCH encoder design; linear feedback shift register; sharing sub-expression; tree-type structure; CMOS technology; Circuits; Computer architecture; Cyclic redundancy check; Delay effects; Design methodology; Design optimization; Encoding; Optical fiber communication; Polynomials;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design and Video Technology, 2005. Proceedings of 2005 IEEE International Workshop on

Print_ISBN

0-7803-9005-9

Type

conf

DOI

10.1109/IWVDVT.2005.1504560

Filename

1504560