Scalable I/O architecture for buses

The author discusses current IEEE activities on the P1394 bus standard (1 Mb/s) and the P1596 interconnect (1 Gb/s), which concern the definition of standard control register locations, formats, and functions. This scalable definition, called an I/O architecture, is being considered for use by other bus standards as well (P896.1 Futurebus and the P1014 VME bus standards). The scalable I/O architecture definition is bus-technology-independent, and supports large multiple-bus configurations. Several of the scalable features of the I/O architecture are described.<>