Potentialities of silicon piezoresistivity for mechanical state monitoring of VDMOS transistors

Control of reliability is a major economic and technical challenge for power electronics. Today, models can be used to predict failure, but to be accurate this models should be updated continuously by the real mechanical state of the device. A possible solution is to make use of the silicon piezoresistive properties of MOS gated power devices (LDMOS, VDMOS, ...) and to take advantage, without increasing silicon area, of the impact of mechanical stress on the MOS section electrical characteristics to access to the information of mechanical stress value. However, the electrical characteristics are also very sensitive to temperature. This paper discusses the combined effect of temperature and mechanical stress on MOS transistors I(V) characteristics.