• DocumentCode
    1937028
  • Title

    The Sequoia approach to high-performance fault-tolerant I/O

  • Author

    Mark, P.B.

  • Author_Institution
    Sequoia Syst. Inc., Marlboro, MA, USA
  • fYear
    1989
  • fDate
    Feb. 27 1989-March 3 1989
  • Firstpage
    565
  • Abstract
    Summary form only given. The Sequoia computer utilizes a modular, tightly-coupled multiprocessor architecture, with hardware fault detection and software fault recovery to achieve high degrees of reliability, availability, and data integrity. The computer comprises from one to 64 processor elements (PE), and from two to 128 memory elements (ME) and I/O processing elements (IOE). Configurations can be tailored to meet the needs of the applications. Each processor element consists of two CPUs running in lockstep, with 256 kb of non-write-through cache. The non-write-through cache is the foundation of the fault-tolerant operation of the system. Each processor performs its work locally within its cache, periodically checkpointing its state to main memory. Each memory element consists of 16 Mb of memory, protected by ECC (error checking and correction), and 1024 test-and-set locks used to synchronize processor updates to shared data structures within the operating system. Writable data is shadowed in main memory; the data is stored on two different memory elements. Each I/O processing element consists of CPUs running in lockstep, with 2 Mb of local memory. The I/O processors are connected to an IEEE-standard 796 bus (the Multibus), which serves as an I/O bus connecting the IOE to up to 16 peripheral controllers of any type.<>
  • Keywords
    fault tolerant computing; multiprocessing systems; 16 Mbyte; I/O processing element; IEEE-standard 796 bus; Multibus; Sequoia approach; availability; data integrity; error checking and correction; hardware fault detection; high-performance fault-tolerant I/O; reliability; software fault recovery; tightly-coupled multiprocessor architecture; Application software; Availability; Checkpointing; Computer architecture; Error correction codes; Fault detection; Fault tolerance; Fault tolerant systems; Hardware; Protection;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    COMPCON Spring '89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, Digest of Papers.
  • Conference_Location
    San Francisco, CA, USA
  • Print_ISBN
    0-8186-1909-0
  • Type

    conf

  • DOI
    10.1109/CMPCON.1989.301994
  • Filename
    301994