Title :
A distributed-RCL model for MCM layout
Author :
Zhou, D. ; Tsui, F. ; Cong, J.S. ; Gao, D.S.
Author_Institution :
Dept. of Electr. Eng., North Carolina Univ., Charlotte, NC, USA
Abstract :
The authors model high-speed VLSI interconnects by using a generic distributed RLC-tree. Through a detailed analysis of the distributed RLC-tree a two-pole approximation system is established to formulate the performance-driven layout in MCM designs. An in-depth study of the formulated performance-driven layout problem reveals the interplay between the interconnector´s performance and its geometrical parameters. The study leads to an A-tree topology to optimize the defined performance-driven layout problem. Significant improvement, an average up to 67% reduction on the interconnection delay, is achieved over large sample MCM designs, as compared with the well known Steiner tree topology
Keywords :
VLSI; circuit layout CAD; distributed parameter networks; multichip modules; network routing; network topology; trees (mathematics); A-tree topology; MCM designs; MCM layout; Steiner tree topology; distributed-RCL model; generic distributed RLC-tree; geometrical parameters; high-speed VLSI interconnects; interconnection delay; optimisation; performance-driven layout; routing; transmission line; two-pole approximation system; CMOS technology; Distributed parameter circuits; Driver circuits; Integrated circuit interconnections; RLC circuits; Semiconductor device modeling; Sun; Very large scale integration; Voltage; Wire;
Conference_Titel :
Multi-Chip Module Conference, 1993. MCMC-93, Proceedings., 1993 IEEE
Conference_Location :
Santa Cruz, CA
Print_ISBN :
0-8186-3540-1
DOI :
10.1109/MCMC.1993.302128
